IBM Nanostack Signals the Next Phase of AI Silicon Scaling

IBM has introduced a research platform for the 0.7 Nanometer (nm), or 7 angstrom, process generation. Its Nanostack architecture joins two separately fabricated wafers through ultra-thin dielectric bonding and distributes nanosheet transistors across vertical tiers rather than placing them side by side. This reduces the area occupied by Complementary Metal-Oxide-Semiconductor (CMOS) logic, while allowing the upper and lower transistors to use different materials and electrical characteristics.

IBM reports nearly 100 billion transistors within a fingernail-sized area, approximately twice the density of its 2 nm research technology. The company projects approximately 50% area scaling, up to 50% higher performance at the same power, or roughly 70% lower power at the same performance. IBM has also demonstrated 40% area scaling for Static Random-Access Memory (SRAM), which could allow future processors to incorporate larger local caches and buffers and reduce the energy and bandwidth required to move Artificial Intelligence (AI) data to external memory. These results establish a potentially significant scaling path for future silicon development, with accelerator—and workload-level testing representing the next step in determining how much of the benefit carries into commercial products.

Nanostack is being developed within IBM’s wider semiconductor research ecosystem at the Albany NanoTech Complex. ASML has stated that it is engaged early in the architecture’s development, with High Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography providing the resolution and process control required for future sub-1 nm manufacturing. Lam Research has similarly described Nanostack as meaningful progress in Three-Dimensional (3D) logic scaling. IBM also works with Lam Research, Tokyo Electron, and SCREEN on supporting High-NA EUV processes and equipment. However, it has not announced that a foundry or processor partner has committed to commercial Nanostack production.

IBM is not alone in exploring vertical transistor scaling. Intel has demonstrated stacked Complementary Field-Effect Transistors (CFETs) with backside power delivery, while imec includes CFET architectures in its longer-term logic roadmap, and Taiwan Semiconductor Manufacturing Company (TSMC) has disclosed related CFET and 3D integration research. Although these approaches differ from Nanostack, they show that several leading semiconductor organizations are investigating vertical transistor architectures for future process generations. IBM expects a path toward initial Nanostack adoption within 5 years.

The scaling opportunity presented by Nanostack is primarily transistor-density and standard-cell-area scaling: fitting more logic and SRAM into a given die area by arranging transistors vertically. This differs from stacking completed chiplets within a package or simply shrinking an individual transistor feature. AI accelerators combine matrix engines, local memory, scheduling logic, and data-movement hardware within constrained die-area and power envelopes. Greater transistor density could allow vendors to add more of these resources or deliver comparable performance using less area and power. Separately optimizing the two transistor tiers could also support different electrical characteristics for performance-sensitive and lower-leakage circuits. The approach reflects an industry shift from relying primarily on lateral transistor shrinkage toward combining vertical device integration, denser local memory, backside power delivery, chiplets, and advanced packaging to sustain AI processor improvements.

AI accelerators and High-Performance Computing (HPC) processors present the clearest potential applications because their designs are increasingly constrained by die area, power, memory bandwidth, and data movement. The more useful question is which constraint this relieves. Today's AI accelerator designs run into three overlapping limits: the energy and latency cost of moving data between compute and memory (the "memory wall"), package- and rack-level power and thermal ceilings that increasingly cap how much compute can be deployed regardless of transistor count, and reticle-driven die-area limits that are already pushing designs toward chiplets rather than ever-larger monolithic logic. Nanostack's disclosed gains map unevenly onto these. The SRAM density and power figures speak directly to the first two: more cache held close to compute reduces trips to external memory, and any power reduction at matched performance eases a rack-level constraint that now limits deployable compute independent of how many transistors a chip holds. Logic density is a weaker match. Leading accelerator designs are already reticle-limited and moving toward multi-die packaging rather than larger single dies, so added transistor density is more valuable as a way to grow local memory or shrink a given design's footprint than as a route to a bigger monolithic accelerator. That distinction is the real test: Nanostack's clearer value proposition to current AI hardware roadmaps is a memory-hierarchy and power one, which will matter most to architectures already built around keeping data close to compute.

IBM’s SRAM demonstration matters within today’s constrained memory market. Micron expects Dynamic Random-Access Memory (DRAM) and NOT-AND (NAND) supply conditions to remain tight beyond 2027, while larger models, longer context windows, and greater inference concurrency are increasing demand for memory capacity and bandwidth. Additional on-chip SRAM could retain frequently accessed data closer to compute, improving data reuse and reducing some High-Bandwidth Memory (HBM) traffic and data-movement energy. It would not replace the capacity of HBM, but it could help vendors build a more balanced memory hierarchy. This direction is already visible in Cerebras’ use of distributed SRAM and SambaNova’s combination of SRAM, HBM, and Double Data Rate (DDR) for different inference data requirements.

Nanostack is part of a wider change in how the semiconductor industry is approaching future scaling. Intel, imec, and TSMC are developing monolithic CFETs that vertically stack n-type and p-type devices through a different fabrication route, while backside power delivery, chiplets, and advanced packaging are already moving other processor components into the third dimension. Vertical transistors could increase density within individual dies, while chiplets and packaging connect those dies into larger systems. Future AI performance gains will depend less on process-node shrinkage by itself and more on the combined optimization of transistor architecture, memory hierarchy, power delivery, interconnect, and packaging. Nanostack matters as evidence of this market transition, even if IBM’s specific implementation does not become the dominant approach.

This transition could change how progress in future AI processors is measured and where architectural differentiation occurs. IBM’s approach is distinctive because its separately fabricated tiers could increase logic and SRAM density while allowing performance-sensitive and lower-leakage circuits to be optimized differently. However, the value of this flexibility will depend on whether it produces greater workload throughput and performance per watt once memory bandwidth, power delivery, thermal limits, interconnect, and software utilization are considered. Future competition may center less on reaching the smallest nominal process node and more on how effectively foundries and processor developers combine transistor architecture with memory, packaging, and system design. Nanostack expands the range of technologies available for that transition, even though it remains too early to determine whether IBM’s implementation will become the preferred route.

Silicon vendors should treat Nanostack less as a standalone IBM product decision and more as one data point inside a transition already underway across Intel's and imec's CFET research, backside power delivery, chiplets, and advanced packaging: competition is shifting from a single-axis race to the smallest process node toward a multi-axis contest over how transistor architecture, memory hierarchy, power delivery, and packaging combine around each processor's actual bottleneck. New transistor architectures rarely earn commercial standing on a density figure alone. The typical route runs from early equipment and tooling alignment, already visible here through ASML and Lam Research, to a foundry or processor developer committing die area to a workload-representative proof of concept, to a roadmap connecting that result to commercial silicon. Nanostack has cleared only the first of those stages, so the first concrete signal to watch is a named commercial partner: a processor developer or foundry committing to a test chip would say more about Nanostack's trajectory than any further density or power disclosure from IBM.

The second signal is how far IBM pushes Nanostack's reach. A density advantage confined to IBM's own manufacturing environment and a narrow set of bilateral partners caps the return on the underlying research, since design-tool support and Intellectual Property (IP) licensing are easier to justify across many customers than a few. IBM has a clear incentive to make Nanostack as portable as possible across manufacturing environments and processes, and its licensing choices, whether they point toward a broad, open model or a closed bilateral one, are worth tracking closely. A narrower path is not automatically a failure: a technology confined to the most density-constrained, highest-value accelerator segment can still be commercially credible if the performance-per-watt advantage justifies the added complexity for that segment alone. What to watch for is the direction IBM leans, because it changes depending on where a given vendor sits; a broad, portable model lowers the switching cost of designing around Nanostack down the line, while a narrow, bilateral one signals that only a small set of partners will get early access to whatever advantage it delivers.

The broader takeaway splits into what and who are worth watching. For silicon vendors, the stakes are about timing: whoever first converts vertical transistor integration into a workload-proven, economically viable system resets the performance-per-watt and density baseline the rest of the market has to design against, and design-tool and IP ecosystems tend to consolidate quickly around whichever approach gets there first: Intel, imec, and TSMC's parallel CFET work means Nanostack is not the only candidate for that role. Vendors that track these signals closely have more room to decide whether to design around an eventual vertical-integration partner, invest in their own path, or wait; vendors that don't risk finding the ecosystem already built around someone else's architecture.

For IBM, the more useful takeaway is that reusability is the real multiplier on Nanostack's value: the more foundries, processes, and product segments it can support beyond IBM's own manufacturing environment, the more reason design-tool vendors, IP providers, and processor developers have to invest in supporting it. That is what converts a strong research result into an industry input, even at the cost of a diluted performance edge on any single implementation. A broad, imperfect footprint would do more for Nanostack's commercial trajectory than a narrower one confined to a small set of high-performance partners.