The Custom Silicon Paradox: Winning More, Capturing Less?

In August 2026, MediaTek expanded its NVIDIA partnership to include NVLink Fusion, giving customers a prevalidated foundation for integrating custom Artificial Intelligence (AI) accelerators into NVIDIA’s rack-scale infrastructure. The platform incorporates qualified NVLink chiplets, NVLink Chip-to-Chip (C2C), and NVIDIA High Bandwidth Memory (NVHBM) technologies, reducing some of the engineering and validation work associated with custom accelerator deployment. NVIDIA also invested US$3.5 billion in MediaTek through convertible bonds, reinforcing the companies' collaboration.

At its October 2026 briefing, MediaTek positioned NVLink Fusion alongside its end-to-end custom Application-Specific Integrated Circuit (ASIC) services. NVLink Fusion emphasizes deployment speed and lower integration risk, and the end-to-end offering gives customers greater architectural control over compute, memory, and Input/Output (I/O). MediaTek is targeting more than US$2 billion in AI data center ASIC revenue in 2026, positioning itself as an emerging competitor to Broadcom and Marvell. The move follows a diversification of custom silicon strategies. Marvell is expanding its semi-custom XPU-attach portfolio, and Broadcom pursues architectural co-design through multigenerational accelerator programs with Google, Meta, and OpenAI.

Wider availability of prevalidated AI infrastructure could change the economics of successive custom accelerator programs. NVLink Fusion lets customers develop custom XPUs on a timeline separate from the surrounding rack infrastructure, reducing some of the integration and deployment risks associated with introducing new architectures. It is expected that the immediate opportunity will come from additional workload-specific designs at established hyperscalers, with limited expansion into smaller enterprise customers. These hyperscalers already operate at the scale needed to justify custom silicon, and infrastructure reuse could make additional accelerator architectures easier to justify economically.

Standardization could strengthen hyperscalers’ negotiating positions before it leads to meaningful supplier switching. Custom ASIC relationships have historically relied on extensive engineering integration, making it costly to change design partners between generations. Customers retaining ownership of their compute architectures and reusing established infrastructure interfaces could open future development contracts to competitive bidding. Hyperscalers may increasingly separate proprietary accelerator implementation from previously qualified infrastructure components, giving them grounds to challenge the engineering scope and Non-Recurring Engineering (NRE) costs proposed by incumbent suppliers. Competitive pressure could therefore emerge in contract pricing before becoming visible in supplier market share. MediaTek may be particularly exposed to this pressure as it establishes its hyperscaler business, given that NVLink Fusion provides a common integration foundation for competing ASIC design partners without guaranteeing retention across subsequent accelerator generations.

This creates a potential gap between custom silicon revenue growth and supplier profitability. Prevalidated infrastructure could allow design partners to support more programs with fewer incremental engineering resources, and hyperscalers may expect those efficiencies to be reflected in commercial terms. Suppliers relying primarily on implementation services could face greater pressure to justify their proprietary contributions, particularly when competitors can use the same infrastructure foundation. Some suppliers may retain multigenerational customer engagements while capturing a smaller share of the engineering value in successive designs. Design-win retention alone may become a weaker indicator of competitive strength. For MediaTek, this creates a potential trade-off between expanding its custom ASIC pipeline through NVLink Fusion and retaining opportunities to monetize proprietary integration technologies that customers may instead source through NVIDIA's ecosystem.

Several factors limit the extent of this development:

• Technical and Software Integration: Rack-level standardization does not eliminate the complexity of physical design, advanced packaging, memory integration, and manufacturing qualification. Software optimization and performance validation across multiple XPU architectures remain barriers, particularly outside hyperscalers. Google’s recent integration of Tensor Processing Units (TPUs) with open-source frameworks such as virtual Large Language Models (vLLMs) demonstrates the engineering to support broader deployment.
• Incumbent Advantages: Established suppliers retain advantages through accumulated engineering expertise and proprietary Intellectual Property (IP). Broadcom’s multigenerational relationships demonstrate the value of architectural co-design, and Marvell’s XPU-attach strategy offers another model built on reusable proprietary IP that supports multiple accelerator architectures.
• Supplier Economics: Marvell has indicated that its XPU-attached products generally carry richer gross margins than full-custom XPUs. MediaTek's dual approach introduces another consideration, as supporting both prevalidated and end-to-end custom architectures requires engineering resources across different levels of integration. The company will need to demonstrate whether the additional customer opportunities and reuse of engineering capabilities justify both approaches.

The longer-term implication is a redistribution of negotiating power across the custom silicon ecosystem. Hyperscalers could gain flexibility over future accelerator implementations, potentially increasing their dependence on NVIDIA’s infrastructure roadmap. However, this flexibility may remain concentrated among hyperscalers with the software expertise to integrate and validate workloads across multiple XPU architectures. Google's efforts to support TPUs through open-source serving frameworks such as vLLMs illustrate the additional software requirements that could limit custom silicon adoption among smaller cloud providers. Suppliers retaining proprietary memory, connectivity, or processing technologies across multiple XPU generations may preserve stronger commercial positions, with software enablement and validation support providing additional opportunities for differentiation. The next phase of custom silicon competition may depend on how much hardware and software engineering value suppliers retain as infrastructure becomes reusable, making the number of design wins a less reliable measure of strength.

Custom ASIC providers should evaluate how infrastructure reuse changes the engineering responsibilities and commercial value of their engagements. MediaTek should evaluate whether its dual approach to custom ASIC development provides sufficient differentiation as infrastructure becomes more standardized. NVLink Fusion offers deployment advantages, but its availability to competitors including Marvell, Alchip, and GUC limits the value of ecosystem compatibility alone. MediaTek's end-to-end custom services preserve opportunities for deeper architectural involvement, although supporting both approaches requires continued investment in engineering and qualification.

Data center ASICs are expected to be slightly dilutive to corporate gross margins, so MediaTek should demonstrate how its dual custom ASIC strategy provides differentiation beyond NVLink Fusion compatibility, which competing suppliers also offer. The company should prioritize reusable IP, memory integration, and manufacturing capabilities that improve development efficiency and support successive design wins. With data center ASICs expected to dilute corporate gross margins slightly, MediaTek must demonstrate that these capabilities and its software integration expertise can improve long-term profitability.

Suppliers should also evaluate design wins according to expected multigenerational profitability and projected accelerator shipments. Marvell's growing XPU-attach business illustrates the opportunity to retain semiconductor content across different accelerator architectures. NVIDIA's expansion into memory and interconnect technologies could compete with portions of that opportunity. Broadcom's co-design approach provides another model where customer-specific performance improvements justify greater engineering involvement. Both strategies will depend on retaining proprietary value as customer architectures evolve.

For hyperscalers, standardized infrastructure creates an opportunity to reassess which components require proprietary development and which can be reused across accelerator generations. Greater flexibility over ASIC design partners should be weighed against potential dependence on the underlying infrastructure provider. Investors and industry analysts should also examine Non-Recurring Engineering (NRE) structures, supplier-owned IP, production profitability, and follow-on contract terms when evaluating design-win announcements. The commercial value of successive design wins will become an increasingly important measure of custom silicon competitiveness, even where customer relationships and reported market shares remain stable.