When Autonomy Meets Autonomy: The Compute Shift in Counter-Defense

Lockheed Martin demonstrated its Coordinated Autonomous Remote Intercept (CARI) system at the U.S. Army's Technology Readiness and Experimentation exercise in September 2026, using an autonomous defensive swarm to respond to an incoming Unmanned Aerial Vehicle (UAV) swarm. CARI combines Lockheed Martin's Sanctum counter-Unmanned Aircraft System (UAS) sensor-processing suite, anchored by a Fortem R30 radar, with onboard autonomy and a Command and Control (C2) and swarm-management layer that calculates defensive formations and assigns tasks across the interceptor swarm. The defensive UAVs autonomously launched and formed a Three-Dimensional (3D) barrier that adapted as the opposing swarm moved, accelerated, or split apart. The system stayed operational when two UAVs temporarily lost connectivity, a resilience test worth flagging. Lockheed Martin also built the autonomy software to run across different airframes, so the interceptor layer can be swapped or upgraded without changing the wider defensive architecture. For semiconductor suppliers, the significance is the processing chain behind the swarm: persistent sensing, low-latency fusion, distributed C2, and onboard autonomy place different compute requirements across the defensive architecture.

CARI reflects a broader market shift, moving from countering individual remotely operated drones toward responding to larger numbers of coordinated and increasingly autonomous systems. As threat volume climbs, the scaling problem migrates toward the front of the defensive chain: detecting small objects, maintaining tracks, correlating observations across sensors, separating threats from clutter, and prioritizing which targets need a response before the engagement window closes. Joint Interagency Task Force (JIATF)-401 is already questioning whether counter-UAS architectures require fire-control-quality sensing at every location and is leaning toward broader use of lower-cost commercial and dual-use sensors whose outputs get combined at the system level. That thinking is also pushed beyond reliance on conventional Radio Frequency (RF) detection toward radar, optical, acoustic, and other physical signatures. JIATF-401 has specifically pointed to cameras and radar as increasingly important as the market moves away from reliance on RF alone. This puts the strongest near-term compute requirement on persistent sensing and tactical fusion, where radar, RF, and Electro-Optical/Infrared (EO/IR) inputs must become reliable tracks before an autonomous effector can be useful. Sensor density matters for a related reason: expanding defended coverage generates semiconductor demand across more sensing and preprocessing nodes, even when each node runs modest Artificial Intelligence (AI) compute.

Defense also changes what matters in the underlying hardware. Unlike most commercial edge AI deployments, counter-autonomy has to support workloads that can change in response to an adversary. A sensing method, classifier, communications signature, or flight profile that works today can become less useful once the opposing system changes its behavior. In contrast, communications and Positioning, Navigation, and Timing (PNT) may be degraded by design rather than by accident. JIATF-401 has indicated that drone developments and subsequent countermeasures can emerge on cycles of less than four weeks, faster than conventional military hardware replacement timelines can accommodate. A 4-week threat cycle does not imply a 4-week silicon cycle. At that cadence, adaptation has to occur primarily in software-defined portions of the system, including RF libraries and waveforms, classification models, tracking and fusion logic, and sensor tasking. At the same time, the underlying hardware remains in service. This increases the value of compute headroom, flexible Input/Output (I/O), reconfigurable logic, and memory capacity that can support several generations of algorithms without a board redesign. Current Army counter-UAS requirements also call for limited active radar emissions and greater use of passive operation, because the defensive sensor can itself become part of the adversary's targeting cycle. These conditions increase the value of compute headroom, reprogrammability, sensor I/O, detection-to-track latency, simultaneous track capacity, fusion confidence, sensor-to-effector latency, and software deployment speed, while lowering the relevance of standalone Tera Operations per Second (TOPS). Mission-critical autonomy still depends on assured behavior and deterministic control; counter-autonomy adds the requirement to update the sensing and processing stack fast enough to keep pace with an adapting threat.

The result is a tiered-edge compute architecture rather than a single accelerator market. At the sensor edge, Digital Signal Processors (DSPs), Field-Programmable Gate Arrays (FPGAs), Neural Processing Units (NPUs), and dedicated accelerators can handle radar, RF, or vision preprocessing within tight latency and power budgets. For example, a distributed radar node can use an adaptive System-on-Chip (SoC) or FPGA to digitize RF inputs, perform beamforming, Fast Fourier Transforms (FFTs), filtering, and early track processing locally, then send track metadata rather than raw RF data to the fusion layer. In that use case, deterministic latency, sensor I/O, and programmability can matter more than peak TOPS because reducing data movement and producing a usable track sooner improves the wider system’s response time. Tactical fusion nodes can carry larger Central Processing Units (CPUs), AI accelerators, and memory resources to correlate tracks and maintain state across multiple sensors. At the same time, the interceptor remains constrained by Size, Weight, Power, and Cost (SWaP-C). It may only need enough local processing for navigation, perception, control, and degraded-network operation.

For silicon vendors, this increases the value of software portability and long-lived compute interfaces: a processor architecture supported across multiple airframes can carry a design win beyond one platform. However, modularity also makes that position easier for competing hardware to displace. Memory requirements also diverge across these layers. Sensors and interceptors need to fit models, state, and buffers within constrained local memory. In contrast, fusion nodes increasingly need capacity and bandwidth to hold multiple sensor streams, track histories, model weights, and intermediate data without creating a new bottleneck between sensing and compute. Stable functions such as filtering, beamforming, and portions of radar processing can benefit from dedicated acceleration, while classification, fusion, Electronic Warfare (EW) processing, and target prioritization require greater software flexibility. The semiconductor opportunity is more likely to scale through a growing number of heterogeneous sensing and fusion nodes than through continuously increasing processor performance on every autonomous platform.

Semiconductor vendors targeting counter-autonomy should treat sensor processing and tactical fusion as the primary near-term opportunity. Assuming that greater autonomy automatically creates a large market for increasingly powerful processors aboard individual interceptors misplaces the emphasis. Every protected location requires persistent awareness, while an autonomous interceptor is only one of several possible effectors and often needs to remain inexpensive enough to preserve the cost exchange against lower-cost threats. JIATF-401 is already trying to aggregate demand across commercial and defense buyers and has used small-form-factor radar as an example of a market that could reach billions of dollars in annual demand if procurement signals are visible early enough. Vendors should therefore demonstrate complete sensing-to-response pipelines that ingest radar, RF, and EO/IR data concurrently and report detection-to-track and sensor-to-response latency alongside probability of detection, false-alarm rate, concurrent track capacity, memory use, and system power. TOPS is a poor proxy for field value in counter-autonomy. A lower-TOPS processor that produces reliable tracks faster, consumes less power, and sustains multiple sensor inputs can create more value than a larger accelerator optimized around an isolated AI inference benchmark.

Semiconductor suppliers should also avoid over-specializing the threat-dependent portion of the compute stack. Counter-autonomy is an adversarial workload, and hardware designed too tightly around today's classifier, RF signature, or sensing method risks losing value well before the end of the platform's hardware lifecycle. Fixed-function acceleration should be concentrated around stable operations where its efficiency remains useful. At the same time, threat classification, sensor fusion, EW processing, and other changing functions should stay programmable wherever SWaP-C permits. This gives CPUs, GPUs, and particularly FPGAs or adaptive compute a stronger position at the sensing and fusion layers than they may hold in less adversarial edge markets, provided vendors can simplify software development and support AI workloads rather than relying on programmability alone. A processor that can absorb a new sensor, waveform, or model within weeks may create more military value than a more efficient architecture that requires a hardware redesign. Semiconductor vendors should sell counter-autonomy around time-to-update and complete workload performance, not only peak compute efficiency.

Open interoperability should also be treated as a market-access requirement rather than a product differentiator. Counter-autonomy is developing as a system of systems in which radar, passive RF, EO/IR, C2, AI software, and effectors are unlikely to come from one supplier. JIATF-401 has explicitly argued for modular open architectures and common interfaces. At the same time, current Army evaluations require technical interoperability with Forward Area Air Defense Command and Control (FAAD C2), the Integrated Sensor Architecture (ISA), or equivalent standards. Semiconductor and module suppliers that require tightly coupled proprietary sensor formats or software stacks risk being designed out as governments prioritize rapid technology insertion. The strongest semiconductor position in counter-autonomy will not belong to the vendor with the largest accelerator; it will belong to the supplier that becomes the adaptable processing layer between changing sensors, algorithms, and effectors.