Is Hardware Acceleration Necessary for Open RAN mMIMO Success?

5G networks are currently enabled through complex and highly integrated mobile infrastructure that includes computationally intensive Massive Multiple Input, Multiple Output (mMIMO), higher frequency bands, and a complex Physical (PHY) layer configuration. The processing in Open Radio Access Network (Open RAN) is split between the Open Centralized Unit (O-CU), Open Distributed Unit (O-DU), and Open Radio Unit (O-RU), and these computational requirements increase with the number of subscribers, bandwidth, and number of antennas. In traditional network infrastructure, developed by legacy vendors, these processing requirements have been fulfilled by custom, specialized processors that have been designed for these payloads. These are often in the form of Application Specific Integrated Circuits (ASICs) that take years to design, develop, and manufacture in large quantities. General Purpose Processors (GPPs) are now starting to be used in cellular network infrastructure, such as x86 processors, aiming to replace custom silicon with Custom Off-the-Shelf (COTS) processors.

However, there are concerns that using only GPPs to fulfill computation requirements of Open RAN may lead to performance degradation, higher power consumption, and increased cost. In order to solve this problem, hardware acceleration has been proposed for Open RAN that offloads complex and time-sensitive workloads to specialized hardware accelerators such as Data Processing Units (DPUs), Graphics Processing Unit (GPU), Digital Signal Processors (DSPs)/Systems-on-Chip (SoCs), ASICs, and Field Programmable Gate Arrays (FPGAs) to enable accelerated computing for Open RAN. This is particularly necessary for mMIMO, where the PHY layer requires heavy computational processes for beamforming and radio layer calculations.

The O-RAN Alliance has developed a framework called the Acceleration Abstraction Layer (AAL) that aims to abstract the RAN software components from accelerators via the AAL interface. This enables flexible and plug-in-play execution of multi-vendor software migration from one accelerator to another device without requiring custom integration. The concept of AAL is based on two key aspects: 1) what to accelerate, and 2) how to accelerate, and they are operated in either look-aside or in-line modes.

Traditionally, RAN acceleration for the PHY layer has been implemented in look-aside mode that requires back-and-forth data transfer between the CPU and the accelerator. In case of multiple and parallel acceleration, the back-and-forth data exchange may increase the Double Data Rate (DDR), resulting in significant bandwidth consumption. One possible solution to overcome the limitations of look-aside acceleration is the in-line mode of acceleration that has emerged as an alternative approach for large-scale deployments. The in-line acceleration mode offloads complete PHY layer processing functions to hardware accelerators, where the output is directly sent toward the Radio Unit (RU) to avoid delays and redundant bandwidth usage between the CPU and the accelerator device. This results in significant Capital Expenditure (CAPEX) and Operational Expenditure (OPEX) savings for mobile operators, and it further scales up with high-capacity mMIMO scenarios. It should be noted that even large legacy infrastructure vendors do not have a consistent strategy for either in-line or look-aside acceleration. Some have chosen one option, whereas some have chosen the other.

Chipset vendors have started to develop full protocol stack solutions adopting GPPs in conjunction with hardware accelerators to perform PHY layer processing. Some major announcements related to this development are as follows:

1. NVIDIA Grace Hopper Superchip: NVIDIA’s Grace Hopper Superchip is designed to eliminate the requirement of custom accelerators, with COTS servers hosting both RAN and Artificial Intelligence (AI) applications. It integrates CPU, GPU, and DPU features within a single chip to provide full-stack acceleration and to improve performance and energy-efficiency of Open RAN.
2. Marvell’s OCTEON 10 Fusion: Marvell’s OCTEON 10 family of baseband processors performs all Layer 2 (L2) and Layer 3 (L3) processing by replacing x86 processors at the DU and is used as a DPU in cloud configurations.
3. Qualcomm X100 In-Line Acceleration Card: Qualcomm X100 is an in-line acceleration card that performs entire 5G PHY layer and offloads CPU cores from latency-sensitive and compute-intensive 5G PHY layer functions (e.g., beamforming, channel coding, and mMIMO computation) to reduce the number of processors and power consumption, and increase the overall system performance.
4. Intel vRAN Boost: Intel’s integrated Virtualized RAN (vRAN) acceleration with the Xeon SoC eliminates the requirement of an external accelerator card, and it is capable of processing all the Layer 1 (L1) acceleration, including high-end mMIMO configurations.

The topic of hardware acceleration for Open RAN has become an important area of research and ABI Research recommends that mobile vendors, operators, and chipset vendors collaborate and contribute to O-RAN Alliance activities related to this development and follow these approaches:

• Super and Integrated Chipsets: One effective solution that is gaining momentum is the design of integrated chipsets that provides full-stack acceleration, including latency-sensitive PHY layer processing for mMIMO without the requirement of external accelerators cards. Another interesting area for future research is to explore the use of hardware acceleration beyond the PHY layer (e.g., L2/L3 processing and AI-based execution in a RAN Intelligent Controller (RIC)). Currently, all major chipset vendors, including NVIDIA, Marvell, Intel, and Qualcomm have started this development, but none of these solutions are being translated into commercial products.
• Adaptation of RISC-V Based Chipsets for Open RAN: ABI Research recommends that the chipset industry adopt RISC-V based designs to enable processor innovation through open collaboration between mobile vendors, operators, and chipset manufacturers. This enables an open-source platform for chipset designs in Open RAN deployments. Currently, there are only a few semiconductor vendors that are collaborating in RISC-V, mainly focusing on small cells and low-powered units. A RISC-V-based chipset has the potential to fulfill the processing requirements of large-scale mMIMO with lower cost and reduced power consumption.
• Accelerate ULPI Development and Standardization: The activities related to mMIMO Uplink Performance Improvement (ULPI) work item in the O-RAN Alliance is under-development and it might take some time before the optimal functional split and RU reference design for Uplink (UL) mMIMO will be finalized. Therefore, it is extremely important to accelerate this development, before the final testing, integration, and standardization processes. Moreover, depending on the new architecture, there will be a need for new protocols and interfaces for hardware acceleration before the widescale commercial deployment of hardware accelerators in Open RAN.

To summarize, there are many options and challenges to resolve, especially when considering silicon for mMIMO Open RAN. However, new infrastructure vendors and startups have many options to implement their algorithms, which will likely create an acceleration wave for the Open RAN market in 2024.